Advances in Computers: Power-Efficient Network-on-Chips: Design and Evaluation, Volume One Hundred Twenty Four, First Edition
- 6h 17m
- Suyel Namasudra
- Elsevier Science and Technology Books, Inc.
- 2022
Advances in Computers, Volume 124 presents updates on innovations in computer hardware, software, theory, design and applications, with this updated volume including new chapters on Traffic-Load-Aware Virtual Channel Power-gating in Network-on-Chips, An Efficient DVS Scheme for On-chip Networks, A Power-Performance Balanced Network-on-Chip for Mixed CPU-GPU Systems, Routerless Networks-on-Chip, Routing Algorithm Design for Power- and Temperature-Aware NoCs, Approximate Communication for Energy-Efficient Network-on-Chip, Power-Efficient NoC Design by Partial Topology Reconfiguration, The Design of a Deflection-based Energy-efficient On-chip Network, and Power-Gating in Networks-on-Chip.
- Contains novel subject matter that is relevant to computer science
- Includes the expertise of contributing authors
- Presents an easy to comprehend writing style
About the Author
Dr. Suyel Namasudra is an assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Agartala, Tripura, India. Before joining the National Institute of Technology Agartala, Dr. Namasudra was an assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Patna, Bihar, India, and a post-doctorate fellow at the International University of La Rioja (UNIR), Spain. He has received Ph.D. degree in Computer Science and Engineering from the National Institute of Technology Silchar, Assam, India. His research interests include blockchain technology, cloud computing, IoT, and DNA computing. Dr. Namasudra has edited 4 books, 5 patents, and 60 publications in conference proceedings, book chapters, and refereed journals like IEEE TII, IEEE T-ITS, IEEE TSC, IEEE TCSS, ACM TOMM, ACM TALLIP, FGCS, CAEE, and many more. He has served as a Lead Guest Editor/Guest Editor in many reputed journals like ACM TOMM (ACM, IF: 3.144), CAEE (Elsevier, IF: 3.818), CAIS (Springer, IF: 4.927), CMC (Tech Science Press, IF: 3.772), Sensors (MDPI, IF: 3.576), and many more. Dr. Namasudra has participated in many international conferences as an Organizer and Session Chair. He is a member of IEEE, ACM, and IEI. Dr. Namasudra has been featured in the list of the top 2% scientists in the world in 2021 and 2022, and his h-index is 25.
In this Book
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Traffic-Load-Aware Virtual Channel Power-Gating in Network-on-Chips
-
An Efficient DVS Scheme for On-Chip Networks
-
A Power-Performance Balanced Network-on-Chip for Mixed CPU-GPU Systems
-
Routerless Networks-on-Chip
-
Routing Algorithm Design for Power- and Temperature-Aware NoCs
-
Approximate Communication for Energy-Efficient Network-on-Chip
-
Power-Efficient Network-on-Chip Design by pArtial Topology Reconfiguration
-
The Design of an Energy-Efficient Deflection-Based On-Chip Network
-
Power-Gating in NoCs
