SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, Second Edition
- 5h 37m
- Peter Flake, Simon Davidmann, Stuart Sutherland
- Springer
- 2006
Reflecting the syntax and semantic changes to the SystemVerilog language, this text explains the SystemVerilog "packages," summarizes the synthesis guidelines presented throughout, and contains code examples using the latest version of the tools.
